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Sobel image edge detector method simulation and implementation on FPGA
This is the final project of my B.Sc. degree. In this project, we have worked on the implementation of Sobel edge detector using Verilog hardware language (without using any IP core or coregen).
Foremost, the selected image converted to gray-scale which means any pixel has a color value between 0 – 255. Then we sweep the blocks of the pixels into a Sobel core and we collect the output data in order to convert them to an image.
Simulation has been done using Modelsim and conversion stages have been performed by the help of Linux graphic libraries like libjpeg,etc.
All the procedures have been taken place under Linux (Ubuntu).
I have explained entire project and codes in my old blog, in this case I direct you to:
“Sobel” method simulation and implementation on FPGA